https://people.inf.ethz.ch/omutlu/pub/mutlu_jan05.pdf
... , S. Fields, H. Le, and B. Sinharoy. POWER4 system microarchitecture. IBM Technical White Paper, Oct ... , S. Fields, H. Le, and B. Sinharoy. POWER4 system microarchitecture. IBM Technical White Paper, Oct ...
https://people.inf.ethz.ch/omutlu/pub/mutlu_sbacpad04.pdf
... . Tendler, S. Dodson, S. Fields, H. Le, and B. Sin- haroy. POWER4 system microarchitecture. IBM Tech- nical ... . Tendler, S. Dodson, S. Fields, H. Le, and B. Sin- haroy. POWER4 system microarchitecture. IBM Tech- nical ...
https://people.inf.ethz.ch/omutlu/pub/bandwidth_lds_hpca09.pdf
... is based on that of the IBM POWER4/POWER5 prefetcher, which is described in more detail in [38, 36 ... is based on that of the IBM POWER4/POWER5 prefetcher, which is described in more detail in [38, 36 ...
https://people.inf.ethz.ch/omutlu/pub/enhanced-memory-controller-fo...
... prefetchers. A stream prefetcher [57] (based on the stream prefetcher in the IBM POWER4 [61]), a Markov ... stream prefetcher [57] (based on the stream prefetcher in the IBM POWER4 [61]), a Markov prefetcher [25 ...
https://people.inf.ethz.ch/omutlu/pub/heterogeneous-block-architect...
https://people.inf.ethz.ch/omutlu/pub/heterogeneous-block-architecture_cmu_safari_tr14.pdf, SAFARI Technical Report No. 2014-001 – March 13, 2014 The Heterogeneous Block Architecture §†Chris Falli...
https://people.inf.ethz.ch/omutlu/pub/qureshi_dsn05.pdf
https://people.inf.ethz.ch/omutlu/pub/qureshi_dsn05.pdf, Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors Moinuddin K. Qureshi Onur Mutlu Yale N....
untitled
... an implementation of an aggressive stream prefetcher (similar to the one used in the IBM POWER4/5 [39 ... an implementation of an aggressive stream prefetcher (similar to the one used in the IBM POWER4/5 [39 ...
https://people.inf.ethz.ch/omutlu/pub/TR-HPS-2005-001.pdf
https://people.inf.ethz.ch/omutlu/pub/TR-HPS-2005-001.pdf, An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors Onur Mutlu Hyesoo...
https://people.inf.ethz.ch/omutlu/pub/acs-TR-HPS-2008-003.pdf
https://people.inf.ethz.ch/omutlu/pub/acs-TR-HPS-2008-003.pdf, An Asymmetric Multi-core Architecture for Accelerating Critical Sections M. Aater Suleman Onur Mutlu Moinuddin Qureshi Yale N. Patt H...
main.dvi
main.dvi, https://people.inf.ethz.ch/omutlu/pub/acs_asplos09.pdf, main.dvi Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures M. Aater Suleman University of Texas at ...
